A known dynamic random access memory (DRAM) cell includes a transistor and a capacitor. The transistor functions as a switch controlling whether a data bit is being written into, read from, or held in the DRAM cell. The capacitor functions as the storage device. This one-transistor/one-capacitor (1T/1C) structure limits the extent to which the DRAM cell can be miniaturized and hence the memory capacity of the DRAM device given a certain physical size. The increasing need for smaller electronic systems and larger memory capacity (such as multi-gigabytes), among other reasons, requires reduction in size of the physical structures inside a memory device. While the minimum size of the transistor has been shrinking with the advance of the semiconductor fabrication technology, the size of the capacitor has become the bottleneck in miniaturization of the DRAM cell.
A capacitor-less DRAM cell technology has been provided by fabricating a metal-oxide semiconductor field-effect transistor (MOSFET) on a silicon-on-insulator (SOI) wafer. Because of the insulator between the MOSFET and the base substrate of the wafer, the body of the MOSFET is electrically floating. This effect is utilized to store data by storing a charge (holes in an n-channel MOSFET, or NMOS) in and drawing the charge out of the floating body, which performs the functions of the capacitor in the typical DRAM cell. Such a “floating body cell”, or FBC, eliminates the need for the capacitor in a DRAM cell, thereby removing the capacitor as a bottleneck in the miniaturization of the DRAM cell. However, SOI devices are more costly to produce and therefore have been used primarily for high-end applications. Thus, to increase memory capacity without substantially increasing the size and the cost of DRAM devices, there is a need for reducing the size of a DRAM cell in a less expensive way.